Currently, high density (greater than 4 megabytes (Mb) of data storage per chip) and high speed bipolar-complementary MOS (BICMOS) and CMOS static random access memories (SRAMs) require memory cell size below 20 .mu.m.sup.2, low standby current, and high cell stability at low operating voltage. Thin Film Transistors (TFT) were proposed as the load device in the memory cell to replace polysilicon load resistors, in order to meet the density, standby current, cell stability, and soft error immunity requirements. However, conventional polysilicon TFTs have high threshold voltage and low mobility, and therefore poor ON current, due to the finite size of polysilicon grains.
Large grains created by recrystallization of amorphous silicon (.alpha.-Si) films have been used to minimize grain boundary scattering to improve ON current, and to reduce generation-recombination at grain boundaries to minimize the OFF current. (See: Kinugawa et al., TFT (Thin Film Transistor) Cell Technology for 4Mbit and More High Density SRAMs, Tech. Dig. of 1990 VLSI Technol. Symp.:23-24 (1990); and Uemoto et al., High-Performance Stacked-CMOS SRAM Cell by Solid Phase Growth Techniques, Tech Dig. of 1990 VLSI Technol. Symp.:21-22 (1990)).
Thinning of the polysilicon layer and the use of double gates (top and bottom) have provided better ON current and ON/OFF current ratio. (See: Adan et al., A Half-Micron SRAM Cell Using a Double-Gated Self-Aligned Polysilicon PMOS Thin Film Transistor (TFT) Load, Tech. Dig. of 1990 VLSI Technol. Symp.:19-20 (1990); and Hashimoto et al., Thin Film Effects of Double-Gate Polysilicon MOSFET, Ext. Abst. of 22nd Conf. on Solid St. Dev. and Mat.:393-396 (1990)). However, the ON current requirement for 4 Mb (or higher) density, high speed (sub 5 ns) SRAMs is difficult to meet with Si TFTs because of mobility limitations and the lack of grain size uniformity control. What is desired is a TFT with a high carrier mobility.
Other materials, such as germanium, have different energy band structures resulting in higher carrier mobilities. Such higher carrier mobilities are desirable because the mobility of carriers ultimately determines the switching speed of the device. The faster the switching speed, the more operations the given device can perform within a given unit of time.
Silicon-germanium (SiGe) alloys can be grown on a Si substrate so long as the alloy layer is sufficiently thin. See, T. P. Pearsall et al., Enhancement- and depletion-mode p-channel Ge.sub.x Si.sub.1-x modulation doped FETs, IEEE Electron Device Letters, EDL-7: 308-310 (1986), and R. C. Taft et al., Fabrication of a p-channel BICFET in the Ge.sub.x Si.sub.1-x /Si system, International Electron Device Conf. Digest: 570-573 (1988). Because the lattice spacing of a crystal of Ge is larger than the lattice spacing of a crystal of silicon, a layer that includes an alloy of Ge and Si is placed under strain when grown. The Ge crystal lattice is compressed and provides a so-called pseudomorphic layer. See E. Kasper, Growth and Properties of Si/SiGe Superlattices, MSS-II Proceedings, Kyoto, Japan: page 703 (September 1975); D. V. Lang, Measurement of the Band Gap of Ge.sub.x Si.sub.1-x /Si Strained Layer Heterostructures, Applied Physics Letters, 47: page 1333 (1985). With such strained layers, several groups have demonstrated that two-dimensional electron and hole gas layers can be formed. It has recently been shown that the mobility of holes is higher in layers formed of an alloy of Si and Ge than in pure silicon. See, P. J. Wang, et al., Two-dimensional hole gas in Si/S.sub.0.85 Ge.sub.0.15 /Si modulation-doped double heterostructures, Appl. Phys. Lett. Vol. 54, No. 26: page 2701 (1989).
It is possible that the hole mobility in such a system is enhanced by the strain in the alloy layer which decreases the energy of the light hole band relative to the heavy hole band. In such a system, the conduction and valence band discontinuities are relatively low compared to group III-V compound materials. In addition, small Schottky barrier heights on Si would make commercial utilization of the MODFET devices of Pearsall et al. impractical because of a high gate leakage current, particularly at room temperature.
European Patent 0 323 896 AZ discloses a conventional MOSFET device which incorporates a Ge channel region formed of a 90-100% Ge in Si alloy. The channel is symmetric. At each edge of the channel there is an identical transition region from the 90-100% Ge in Si alloy to the surrounding regions of pure Si. Graded regions are provided at each channel edge to accommodate the well known lattice mismatch between Si and Ge, that mismatch being 4.0%. This structure results in the generation of in excess of 10.sup.9 defects per square centimeter in this mostly Ge layer due to the severe mismatch between this layer's lattice constant and that of the Si substrate. Such defects are well known to limit carrier mobility.
Apart from this mechanical consideration, the Ge profile in the channel, as in the prior art, is symmetric and uniform throughout the mostly Ge region. Thus, two active transport regions will be formed at the edges of this channel, one at the transition from the Si substrate to the 90-100% Ge channel, and the other at the transition region back to pure Si at the surface of the device. Each transport region contains a two-dimensional hole gas, centered at each edge of the Ge plateau. Each hole gas has a finite spatial extent, such that half the carriers overlap the defected transition region beyond each plateau edge. This also degrades the mobility of carriers residing in these defected regions. Equally important, hole mobility decreases when holes travel in a region of reduced Ge content, as is the case in prior SiGe channel MOSFET designs.
In U.S. patent application Ser. No. 07/351,630, filed May 15, 1989 and assigned to the same assignee as the present invention, there is disclosed a MOSFET having a SiGe channel layer grown on a Si substrate. A Si cap layer separates the Si dioxide insulator layer from the channel layer. A suitably applied voltage will result in a region of high mobility charge carriers at the interface between the SiGe alloy layer and the Si cap layer. This region will contain a two-dimensional electron or hole gas. By forming the electron or hole gas at the SiGe/Si interface rather than the Si/SiO.sub.2 interface as in previous devices, interface scattering is decreased or eliminated. The region of high mobility charge carriers is as near as possible to the gate (at the Si/SiGe interface), and thus the capacitance is maximized and device performance is enhanced. However, carrier mobility is actually at its lowest nearest the gate. Hence, the device transconductance, which is a figure of merit that is linearly proportional to both capacitance and mobility is not optimized. Furthermore, the channel region described in this earlier work is symmetric as in all known prior devices. The abrupt transitions between Si and SiGe regions in such a symmetric structure result in a number of carriers being transported outside of the channel region.
In U.S. patent application, titled "A Graded Channel Field Effect Transistor," Ser. No. 07/639,625, file Jan. 10, 1991 and now abandoned, and assigned to the same assignee as the present invention, there is disclosed a MISFET having a graded semiconductor alloy channel layer wherein the grading results in the charge carriers being positioned within the channel layer at a location in which transconductance will be optimized. The MISFET includes a strained, pseudomorphic, epitaxial channel layer of an alloy of a first semiconductor material and a second semiconductor material disposed over a substrate. The alloy has a percentage of the second semiconductor material graded within the channel layer to a single peak-percentage level such that the location of carriers within the channel layer coincides with the peak percentage level. An epitaxial cap layer of the first semiconductor material is disposed over the channel layer and a gate insulator layer is disposed over the cap layer. A gate electrode is disposed over the gate insulator layer and source and drain regions are formed in the cap layer and the channel layer on opposite sides of the gate electrode. In one embodiment of the MISFET, the channel layer is formed of a SiGe alloy on a Si substrate.
The channel profile is graded to control the location of the charge carriers in the channel layer to maximize transconductance. The grading results in a built-in electric field which drives the carriers to the desired location in the channel. The graded alloy channel MISFET avoids the problem of the two active transport regions formed in prior devices, as only a single transport region is formed at the location of the single peak-percentage level of the second semiconductor material.
In addition, in prior SiGe channel devices, because the band offset between Si and SiGe is small, a two-dimensional hole gas formed at that interface will spill over into the Si layer, a layer of lesser mobility. In the MISFET, this problem can be avoided by locating the carriers spaced from this interface in order to maintain all or substantially all of the hole gas within the SiGe higher mobility channel. The location of carriers within the channel can be controlled by grading the Ge concentration in Si to a maximum with that maximum being located anywhere in the channel but spaced from either interface. The point of maximum concentration determines the location of the carriers. The particular location within the channel is said to depend on the desired device characteristics.
A additional modulation doping technique is employed in the MISFET device in which the carriers are located below the channel layer. First, a narrow in situ doped boron layer is grown. The total integrated dose, which can be very accurately controlled with low temperature epitaxy, determines the threshold voltage of the device. The doped layer is separated from the SiGe channel by a small undoped spacer, to physically separate the ionized acceptors from the holes in the SiGe channel. Thicker spacers can result in a deleterious parasitic substrate channel.
By modulation doping the channel region of a MISFET, the carriers are physically separated from the ionized atoms, thus allowing high carrier concentrations with negligible ionized impurity scattering and hence high mobilities compared to uniformly doped SiGe MOSFETs. In addition, by locating the dopant below the SiGe channel rather than above as in both the MODFET and the BICFET, the process sensitivity is greatly improved as thinning of the Si cap layer during device fabrication does not affect the total integrated doping and thus the threshold voltage. Compared to the uniformly doped SiGe MOSFET, the parasitic surface channel of the modulation doped device depends much less critically on the Si cap thickness and hence on process variations. The modulation doped device maximizes the ratio of carriers in the SiGe channel over those in both the surface and substrate parasitic channels compared to the uniform SiGe MOSFET. However, the MISFET is a bulk Si device.
The MISFET device itself and the processing therefore do not lend themselves to direct application in thin film devices. It is therefore desirable to provide a TFT device with the operational advantages of the modulation doped MISFET, and can be integrated into high density memories or the like.